The present invention relates to a password-adopted security checking system for the use of, for example, personal computers. Particularly, the present invention relates to a password recognition circuit that supplies the power only to a security check-only partial circuit before supplying the power to the whole of a personal computer. The security check-only partial circuit recognizes as a password the number of times the power switch is depressed and first supplies power to the whole personal computer when the password security checking has passed.
In most conventional information processors with security functions, the security function is performed when the power switch is depressed to supply power to the whole system, thus running a software program for security checking.
JP-A-No. 293626/1998 discloses that when the power switch is turned on, the sub-power unit with computer functions first operates and then begins to check a password. When the checking is passed, the main power unit supplies the power to the whole information processor.
Moreover, according to JP-A No. 333773/1993, when the power switch is depressed while a predetermined combination of keys on the keyboard is been depressed, data corresponding to the depressed keys is compared with a predetermined password. When the data coincides with the password, the system power unit sets up. Thus, the security function is realized without executing a software process.
In these days of placing importance to the protection of private information and the security maintenance within corporations, there are increasing demands for providing the security function to the personal computer itself.
In the above-mentioned conventional technique, inputting passwords or personal identification numbers for the security checking of the information processor depends on entries with a keyboard. Normally, the inputting with the keyboard requires setting up the keyboard driver for a software. In such a case, other device drivers for the software are often made operable so that there is a space for rewriting the security information of invalidating the security protection before the security checking.
In order to avoid such a problem, JP-A-No. 293626/1998 and JP-A-No. 333773/1993 disclose the technique of performing the security checking by a hardware before software itself is set up. Either technique requires a considerable amount of functions to the hardware.
The present invention is made to solve the above-mentioned problems.
Moreover, the objective of the invention is to provide a technique that allows a security checking in a relatively simplified configuration.
According to the first aspect of the present invention, a password recognition circuit comprises a power switch for supplying power to an information processor; a password recognition circuit for first receiving the power when the power switch is depressed, recognizing as a password the number of times the power switch has been sequentially depressed, and deciding whether or not the password coincides with a registered password; a power control circuit for supplying power to the password recognition circuit under first depression of the power switch and receiving a password comparison result from the password recognition circuit, and supplying power to the whole of the system when the password coincides with the registered password or inhibiting power supply to the whole of the system when the password does not coincide with the registered password; and a computer circuit, with a computer function, for receiving power supply from the power control when the password coincides with the registered password.
According to the second aspect of the present invention, a password recognition circuit comprises a return switch for returning an information processor from a suspended mode to a normal operational mode; a password recognition circuit for recognizing as a password the number of times the return switch is depressed sequentially after the return switch has been depressed, and deciding whether or not the password coincides with a registered password; a power control circuit for instructing the password recognition circuit to check the password when first depression of the return switch is recognized, resuming power supply to circuits in a suspended mode when a coincidence of the password occurs in response to a password comparison result by the password recognition circuit, reporting the computer circuit of a coincidence of the password, and reporting the computer circuit of only non-coincidence, without supplying power to the circuits in the suspended mode, when the comparison result does not does not indicate coincidence; and a computer circuit for returning its status from a suspended mode to a normal operation mode when the comparison result indicates coincidence in response to the report from the power control circuit, and issuing a power halt instruction to the power control circuit after the system shutdown process has been performed when the comparison result does not indicate coincidence.
In the password recognition circuit according to the third aspect of the present invention, the password, configured based on the number of times the power switch or the return switch has been depressed, is formed of one or plural digits, the number of times representing one digit corresponding to one of 0 to 9, and wherein a break is inserted between digits at constant time intervals in a depressing operation when the password has plural digits.
In the password recognition circuit according to the fourth aspect of the present invention, the information regarding the password comprises the number of digits of a password, a password in decimal notation, and a time period for inputting one digit of a password.
In the password recognition circuit according to the fifth aspect of the present invention, the password recognition circuit comprises a password memory for storing information regarding the password; a password R/W circuit for accessing the password memory; a password comparator circuit for comparing a password input by the power switch or the return switch with a password stored in the password memory and reporting the power control circuit of coincidence or non-coincidence; a switch operation monitor circuit for counting the number of times the power switch or the return switch has been depressed, based on a time period needed for one-digit entry; and a display control circuit for collecting information regarding displaying an operational status of the switch operation monitor circuit by means of an external device such as a light emitting device.
In the password recognition circuit according to the sixth aspect of the present invention, the power control circuit instructs the password recognition circuit of password verification when the power switch is depressed in a power-suspended mode of the information processor or when the return switch is depressed in a suspended mode of the information processor.
In the password recognition circuit according to the seventh aspect of the present invention, information regarding the password is handled with a password registration program which runs on a computer circuit.